`include "timescale.v"

module tb_apb();
reg 		   	  presetn, pclk, psel, penable, pwrite;
reg  	  [31:0]  paddr;
reg  	  [31:0]  pwdata;

wire 	  [31:0]  prdata;

wire 	  [31:0]  BASE_ADDR;
assign 			  BASE_ADDR   = 32'h8001_0000;

apb apb1(
	.presetn(presetn),
	.pclk(pclk),
	.psel(psel),
	.penable(penable),
	.pwrite(pwrite),
	.paddr(paddr),
	.pwdata(pwdata),
	.prdata(prdata)
	);


always@(posedge pclk or negedge presetn)
begin
  if(!presetn)
	#1 $apb_bridge_reset();
  else
	#1 $apb_bridge(psel, penable, pwrite, paddr, pwdata, prdata);
end

initial begin
  presetn = 0;
  #200 presetn = 1;
end

initial begin
  pclk = 0;
  forever #50 pclk = ~pclk;
end

endmodule // tb_apb
